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CX11656 HomePlug 1.0 PHY
Home Networking Physical Layer Device with Integrated Analog Front End Circuitry
Data Sheet (Preliminary)
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Dissemination, disclosure, or use of this information is not permitted without the written permission of Conexant Systems, Inc.
Doc. No. 102069A August 19, 2002
CX11656 HomePlug 1.0 PHY Data Sheet
Revision Notice
Revision A Date 8/19/2002 Comments Initial release.
(c) 2002 Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant's Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: ConexantTM, the Conexant C symbol, and "What's Next in Communications Technologies"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Conexant's Legal Information posted at www.conexant.com, which is incorporated by reference. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.
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CX11656 HomePlug 1.0 PHY Data Sheet
Contents
1. Introduction ......................................................................................................................................... 1-1
1.1 1.2 1.3 2.1 2.2 3.1 Overview .....................................................................................................................................................................1-1 Features ......................................................................................................................................................................1-3 Applications ................................................................................................................................................................1-3 CX11656 PHY Hardware Interface Signals...................................................................................................................2-1 CX11656 PHY Electrical and Environmental Specifications..........................................................................................2-9 MII Data Interface with MDI Control ............................................................................................................................3-2 3.1.1 MII Interface................................................................................................................................................3-3 3.1.1.1 3.1.1.2 3.1.2 3.1.3 MII Timing Diagram .................................................................................................................3-3 MII Signal Descriptions............................................................................................................3-6
2. Hardware Interface .............................................................................................................................. 2-1
3. CX11656 Functional Description.......................................................................................................... 3-1
3.1.1.3 MII Frame Structure.................................................................................................................3-8 MDI Control Interface ..................................................................................................................................3-9 3.1.2.1 MDI Signal Descriptions ........................................................................................................3-10 MII Management Register Set ...................................................................................................................3-10 3.1.3.1 3.1.3.2 3.1.3.3 3.1.3.4 3.1.3.5 3.1.3.6 PRE (Preamble) .....................................................................................................................3-10 ST (Start of Frame) ................................................................................................................3-10 OP (Operation Code) ..............................................................................................................3-11 PHYAD (PHY Address)...........................................................................................................3-11 REGAD (Register Address).....................................................................................................3-11 TA (Turnaround) ....................................................................................................................3-11
3.2
3.1.3.7 Data .......................................................................................................................................3-11 GPSI Interface with SPI Control.................................................................................................................................3-12 3.2.1 GSPI Interface ...........................................................................................................................................3-12 3.2.1.1 3.2.1.2 3.2.2 GPSI Timing Diagrams...........................................................................................................3-12 GPSI DC Characteristics.........................................................................................................3-14
3.2.1.3 GPSI Signal Descriptions .......................................................................................................3-14 SPI Slave Port Interface.............................................................................................................................3-15 3.2.2.1 3.2.2.2 SPI Slave Port Signal Timing .................................................................................................3-15 SPI Slave Port DC Characteristics ..........................................................................................3-16
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CX11656 HomePlug 1.0 PHY Data Sheet
3.3 3.4 Clocks .......................................................................................................................................................................3-16 AFE Interface .............................................................................................................................................................3-17 3.4.1 ADC/DAC Interface ....................................................................................................................................3-17 3.4.1.1 3.4.1.2 3.4.2 3.5 ADC/DAC Timing Diagrams....................................................................................................3-17 DAC DC Characteristics..........................................................................................................3-19
3.4.1.3 ADC DC Characteristics..........................................................................................................3-19 AGC Circuitry.............................................................................................................................................3-20
3.6
3.4.2.1 AGC DC Characteristics..........................................................................................................3-20 SPI Master Interface..................................................................................................................................................3-21 3.5.1 SPI Master Interface Timing ......................................................................................................................3-21 3.5.2 SPI Master Interface DC Characteristics ....................................................................................................3-21 LED Interface.............................................................................................................................................................3-22
4. Package Dimensions............................................................................................................................ 4-1 5. Application Designs ............................................................................................................................. 5-1
5.1 5.2 5.3 5.4 Ethernet Router Application.........................................................................................................................................5-1 USB Application ..........................................................................................................................................................5-2 Embedded Application.................................................................................................................................................5-3 ADI-Related Components ............................................................................................................................................5-3
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Figures
Figure 1-1. CX11656 HomePlug 1.0 PHY Simplified Hardware Interface..........................................................................1-1 Figure 1-2. CX11656 HomePlug 1.0 PHY Functional Block Diagram................................................................................1-2 Figure 2-1. CX11656 PHY Hardware Interface Signals - 144-Pin LQFP ............................................................................2-2 Figure 2-2. CX11656 PHY Pin Signals - 144-Pin LQFP ....................................................................................................2-3 Figure 3-1. CX11656 PHY Block Diagram ........................................................................................................................3-1 Figure 3-2. MII Data Interface with MDI Control ..............................................................................................................3-2 Figure 3-3. MII TX Waveform ..........................................................................................................................................3-3 Figure 3-4. MII RX Waveform..........................................................................................................................................3-4 Figure 3-5. MII TX with Collision Based on RX Activity ....................................................................................................3-4 Figure 3-6. MII Receive Timing........................................................................................................................................3-5 Figure 3-7. MII Transmit Timing ......................................................................................................................................3-5 Figure 3-8. MII Flow Control Overview, Part 1 .................................................................................................................3-7 Figure 3-9. MII Flow Control Overview, Part 2 .................................................................................................................3-7 Figure 3-10. Partition of Serial Bit Stream to Nibble Stream ............................................................................................3-8 Figure 3-11. MDI Receive Timing ....................................................................................................................................3-9 Figure 3-12. MDI Transmit Timing...................................................................................................................................3-9 Figure 3-13. MDI Frame Structure .................................................................................................................................3-10 Figure 3-14. GPSI Data Interface with SPI Control.........................................................................................................3-12 Figure 3-15. GPSI Flow Control .....................................................................................................................................3-13 Figure 3-16. GPSI Transmit Timing ...............................................................................................................................3-13 Figure 3-17. GPSI Receive Timing .................................................................................................................................3-13 Figure 3-18. SPI Slave Port Timing................................................................................................................................3-16 Figure 3-19. AFE TX and RX Activity ..............................................................................................................................3-17 Figure 3-20. AFE Clock Waveforms................................................................................................................................3-17 Figure 3-21. AFE Transmit Timing Diagram ...................................................................................................................3-18 Figure 3-22. AFE Receive Timing Diagram .....................................................................................................................3-18 Figure 3-23. SPI Master Interface Signal Timing Diagram .............................................................................................3-21 Figure 4-1. Package Dimensions - 144-Pin LQFP.............................................................................................................4-1 Figure 5-1. Ethernet Router Application Block Diagram ...................................................................................................5-1 Figure 5-2. USB Application Block Diagram .....................................................................................................................5-2 Figure 5-3. Embedded Application Block Diagram ...........................................................................................................5-3
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CX11656 HomePlug 1.0 PHY Data Sheet
Tables
Table 1-1. CX11656 HomePlug 1.0 PHY and CX82100-41 Ordering Information.............................................................1-2 Table 2-1. CX11656 PHY Pin Signals - 144-Pin LQFP......................................................................................................2-4 Table 2-2. CX11656 PHY Hardware Signal Definitions.....................................................................................................2-5 Table 2-3. CX11656 PHY DC Electrical Characteristics ....................................................................................................2-9 Table 2-4. CX11656 PHY Operating Conditions ...............................................................................................................2-9 Table 2-5. CX11656 PHY Absolute Maximum Ratings .....................................................................................................2-9 Table 2-6. CX11656 PHY Power Consumption ................................................................................................................2-9 Table 3-1. MII DC Characteristics ....................................................................................................................................3-5 Table 3-2. MI DC Characteristics .....................................................................................................................................3-9 Table 3-3. Powerline Control and Status Register (PLCSR) Summary ...........................................................................3-10 Table 3-4. GPSI DC Characteristics................................................................................................................................3-14 Table 3-5. SPI Slave Command Summary .....................................................................................................................3-15 Table 3-6. SPI Slave Port DC Characteristics .................................................................................................................3-16 Table 3-7. DAC DC Characteristics.................................................................................................................................3-19 Table 3-8. ADC DC Characteristics.................................................................................................................................3-19 Table 3-9. RX Gain Control Values.................................................................................................................................3-20 Table 3-10. AGC DC Characteristics...............................................................................................................................3-20 Table 3-11. SPI Master Interface DC Characteristics......................................................................................................3-21 Table 3-12. LED Interface Signal Description.................................................................................................................3-22
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CX11656 HomePlug 1.0 PHY Data Sheet
1.
1.1
Introduction
Overview
The Conexanta CX11656 device is an integrated physical layer transceiver or PHY (Figure 1-1). It is designed to use existing ac electrical wiring within the home as a networking physical medium. The PHY's robust performance in the electrically noisy power line channel is due to the use of Orthogonal Frequency Division Multiplexing (OFDM). This multi-carrier modulation scheme allows the PHY to dynamically "learn the channel"-- data can be shifted from one carrier to another as real time noise and attenuation conditions change. This overcomes the flaw inherent in previous power line networking technologies--as electrical appliances were turned on and off, changing line conditions caused signal quality to become degraded to such an extent that data transmission became impossible. The CX11656's OFDM technology finds the low noise, low attenuation portions of the spectrum available to it and continues data transmission. The CX11656 is compliant with the HomePlug Powerline Alliance Industry Specification V1.0. This ensures interoperability with other HomePlug PHYs. Quality-of-service (QoS) is built into the PHY to ensure low-latency, high reliability channels for streaming audio, streaming video, voice, and gaming, and video. The PHY utilizes the IEEE 802.3u standard Media Independent Interface (MII). This standard interface can also be configured as a seven-wire General Purpose Serial Interface (GPSI). These standard interfaces allow the CX11656 to be paired almost any embedded media access controller (MAC) for use in a variety of information appliances. The CX11656 operates on both +1.8 V and +3.3 V supplies and is packaged in a 144-pin Low Quad Flat Pack (LQFP). The CX11656 ordering information is listed in Table 1-1. A functional block diagram of the CX11656 is shown in Figure 1-2. Please contact Conexant marketing for information concerning the AFE.
Figure 1-1. CX11656 HomePlug 1.0 PHY Simplified Hardware Interface
Ethernet Interface
802.3 EMAC (e.g., Conexant CX82100)
MII/GPSI Interface
Conexant CX11656 HomePlug 1.0 PHY 144-Pin LQFP
Parallel Interface
Analog Front End*
Coupler
Powerline
* See Section 5.4.
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CX11656 HomePlug 1.0 PHY Data Sheet
Table 1-1. CX11656 HomePlug 1.0 PHY and CX82100-41 Ordering Information
Marketing Order No. HomePlug 1.0 PHY [144-Pin LQFP] Part No. CX11656-11 Home Network Processor (HNP) [196-Pin FPBGA] Part No. CX82100-41
DSHP-L100-001
Figure 1-2. CX11656 HomePlug 1.0 PHY Functional Block Diagram
RESET
CX11656
Interface Block MAC
Power & GND
MDIO Control MDCLK/MDIO - or SPI Control SDI, SDO, SCLK, CS MII RX[3:0], RXCLK, RXDV, RX_ER, TX[3:0], TXCLK, TXEN, TX_ER, COL, CRS - or GPSI RXD, RXCLK, RXEN, TXD, TXCLK, TXEN, COL, TXBSY MII/GPSI Select
Configuration Registers
ROM
ROM
PHY
RISC uProcessor Core MII/GPSI Interface Arbiter PHY Core AFE Interface
Gain Control ADC DAC Interface
DMA & Link Sequencer
Configuration EEPROM Control
EEPROM Control
Buffer RAM
MDIO Address Slect LED Control
CLK IN
LEDS
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1.2
Features
* * * * * * * * * * * * * Single-chip powerline networking controller with IEEE802.3u MII interface Implements the HomePlug Powerline Alliance Industry Specification V1.0 General purpose 7-wire serial PHY data interface Selectable MDI/SPI PHY management interface Up to 14 Mbps data rate on the powerline Orthogonal Frequency Division Multiplexing (OFDM) with patented signal processing techniques for high data reliability in noisy media conditions Intelligent channel adaptation maximizes throughput under harsh channel conditions Integrated quality-of-service (QoS) features such as prioritized random access, contention-free access, and segment bursting 56-bit DES Link Encryption with key management for secure powerline communications EEPROM interface for fast access to configuration parameters allows system designs to leverage standard Ethernet drivers 3.3 V signaling, 5 V tolerant interface Support for three status LEDs 144-pin LQFP package
1.3
Applications
* * * * * * * Residential gateways and home routers Network home or small office PCs Enable no wire installation networking for information appliances LAN gaming Share DSL or cable modem access MDU/MTU applications Embedded applications
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CX11656 HomePlug 1.0 PHY Data Sheet
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2.
2.1
Hardware Interface
CX11656 PHY Hardware Interface Signals
The CX11656 PHY hardware interface signals are shown in Figure 2-1. CX11656 PHY pin signals are shown in Figure 2-2 and are listed in Table 2-1. CX11656 PHY hardware interface signals are defined in Table 2-2.
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CX11656 HomePlug 1.0 PHY Data Sheet Figure 2-1. CX11656 PHY Hardware Interface Signals - 144-Pin LQFP
100 MHz Clock Input 100 MHz Clock Output Reset Control 49 48 44 111 112 CLKIN CLKOUT RESET_N TEST1 TEST2 ADC_CLK DAC_CLK TX_EN RX_EN ADC_CAL AGCENC_N ADIO9 ADIO8 ADIO7 ADIO6 ADIO5 ADIO4 ADIO3 ADIO2 ADIO1 ADIO0 AGC7 AGC6 AGC5 AGC4 AGC3 AGC2 AGC1 AGC0 LED0_N LED1_N LED2_N VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_Q VSS_Q VSS_Q 71 74 76 77 67 69 94 93 92 90 87 86 84 82 81 80 106 105 103 102 100 98 97 96 61 63 65 5 10 19 20 26 30 34 36 41 46 47 55 56 58 62 66 72 75 85 88 101 108 113 117 118 119 127 128 134 138 143 144 9 35 45 70 83 107 142 21 89 130
NC
131 27 29 31 33 22 25 18 4 6 8 11 14 12 16 42 40 135 133 141 137 139 126 59 57 54 52 114 120 124 116 129 1 2 7 13 17 23 24 28 32 37 38 43 50 53 60 68 73 78 99 104 109 115 121 122 123 125 132 140 3 39 64 79 95 110 136 15 51 91
NC MII_RX3 MII_RX2 MII_RX1 MII_RX0 MII_RXCLK/GPSI_RXCLK MII_RXDV/GPSI_TXBSY MII_RX_ER/GPSI_RXD MII_TX3 MII_TX2 MII_TX1 MII_TX0/GPSI_TXD MII_TXCLK/GPSI_TXCLK MII_TXEN/GPSI_TXEN MII_TX_ER MII_CRS/GPSI_RXEN MII_COL/GPSI_COL MII_MDIO/SPIS_SDO MII_MDCLK/SPIS_SCLK MII_GPSI_N MDI_ADRSEL[1]/SPIS_SDI MDI_ADRSEL[0]/SPIS_CS_N MDI_SPIS_N SPI_DO SPI_DI SPI_CLK SPI_CS TCK TDI TMS TDO TRST_N VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_Q VDD_Q VDD_Q
AFE Interface
Shared MMII/GSPI/SPI Interface
AGC IC Interface
LED Interface
SPI Master Port Interface
JTAG Test Interface (Reserved)
CX11656 HomePlug 1.0 PHY 144-PIN LQFP
+1.8 V Core Power
+3.3 V I/O and Quiet Power
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Figure 2-2. CX11656 PHY Pin Signals - 144-Pin LQFP
MDI_ADRSEL[0]/SPIS_CS_N VSS_C MDI_ADRSEL[1]/SPIS_SDI
MII_MDIO/SPIS_SDO VSS_C
MII_MDCLK/SPIS_SCLK VDD_C NC
VDD_IO
VSS_Q TRST_N VSS_C
VSS_C MDI_SPIS_N VDD_C
VSS_IO MII_GPSI_N VDD_C
141 140 139
138 137 136
135 134 133
132 131
144 143 142
130 129 128
127 126 125
124 123 122
VSS_C VSS_C
112 111 110
121 120
119
118 117 116
115 114 113
109
VDD_IO VDD_C
TMS VDD_C VDD_C
VDD_C TDI VSS_C
TDO VDD_C TCK
VSS_C VSS_C
VSS_C TEST2 TEST1
VDD_C VDD_C VDD_IO MII_TX3 VSS_C MII_TX2 VDD_C MII_TX1 VSS_IO VSS_C MII_TX0/GPSI_TXD MII_TXEN/GPSI_TXEN VDD_C MII_TXCLK/GPSI_TXCLK VDD_Q MII_TX_ER VDD_C MII_RX_ER/GPSI_RXD VSS_C VSS_C VSS_Q MII_RXCLK/GPSI_RXCLK VDD_C VDD_C MII_RXDV/GPSI_TXBSY VSS_C MII_RX3 VDD_C MII_RX2 VSS_C MII_RX1 VDD_C MII_RX0 VSS_C VSS_IO VSS_C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 58 59 60 49 50 51 52 53 54 55 56 57 66 67 68 69 70 71 72 61 62 63 64 65
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VSS_C VSS_IO AGC7 AGC6 VDD_C AGC5 AGC4 VSS_C AGC3 VDD_C AGC2 AGC1 AGC0 VDD_IO ADIO9 ADIO8 ADIO7 VDD_Q ADIO6 VSS_Q VSS_C ADIO5 ADIO4 VSS_C ADIO3 VSS_IO ADIO2 ADIO1 ADIO0 VDD_IO VDD_C RX_EN TX_EN VSS_C DAC_CLK VDD_C
CX11656
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VSS_C MII_CRS/GPSI_RXEN
VDD_C VDD_C VDD_IO MII_COL/GPSI_COL
VDD_C RESET_N VSS_IO
VSS_C VSS_C CLKOUT
VDD_Q SPI_CS VDD_C
SPI_DI VSS_C SPI_DO
AGCENC_N VSS_IO
SPI_CLK VSS_C VSS_C
VDD_C LED0_N VSS_C
CLKIN VDD_C
VSS_C ADC_CAL VDD_C
ADC_CLK VSS_C
LED1_N VDD_IO LED2_N
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CX11656 HomePlug 1.0 PHY Data Sheet
Table 2-1. CX11656 PHY Pin Signals - 144-Pin LQFP
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD_C VDD_C VDD_IO MII_TX3 VSS_C MII_TX2 VDD_C MII_TX1 VSS_IO VSS_C MII_TX0/GPSI_TXD MII_TXEN/GPSI_TXEN VDD_C VDD_Q MII_TX_ER VDD_C MII_RX_ER/GPSI_RXD VSS_C VSS_C VSS_Q VDD_C VDD_C MII_RXDV/GPSI_TXBSY VSS_C MII_RX3 VDD_C MII_RX2 VSS_C MII_RX1 VDD_C MII_RX0 VSS_C VSS_IO VSS_C
Signal
Pin No.
37 38 39 40 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD_C VDD_C VDD_IO
Signal
Pin No.
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Signal
VDD_C DAC_CLK VSS_C TX_EN RX_EN VDD_C VDD_IO ADIO0 ADIO1 ADIO2 VSS_IO ADIO3 VSS_C ADIO4 ADIO5 VSS_C VSS_Q ADIO6 VDD_Q ADIO7 ADIO8 ADIO9 VDD_IO AGC0 AGC1 AGC2 VDD_C AGC3 VSS_C AGC4 AGC5 VDD_C AGC6 AGC7 VSS_IO VSS_C
Pin No.
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VDD_C VDD_IO TEST1 TEST2 VSS_C TCK VDD_C TDO VSS_C VSS_C VSS_C TDI VDD_C VDD_C VDD_C TMS VDD_C
Signal
MII_COL/GPSI_COL VSS_C MII_CRS/GPSI_RXEN VDD_C RESET_N VSS_IO VSS_C VSS_C CLKOUT CLKIN VDD_C VDD_Q SPI_CS VDD_C SPI_CLK VSS_C VSS_C SPI_DI VSS_C SPI_DO VDD_C LED0_N VSS_C LED1_N VDD_IO LED2_N VSS_C ADC_CAL VDD_C AGCENC_N VSS_IO ADC_CLK VSS_C
MII_TXCLK/GPSI_TXCLK 50
MDI_SPIS_N VSS_C VSS_C TRST_N VSS_Q NC VDD_C MII_MDCLK/SPIS_SCLK VSS_C MII_MDIO/SPIS_SDO VDD_IO MDI_ADRSEL[1]/ SPIS_SDI VSS_C MDI_ADRSEL[0]/ SPIS_CS_N VDD_C MII_GPSI_N VSS_IO VSS_C VSS_C
MII_RXCLK/GPSI_RXCLK 58
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Table 2-2. CX11656 PHY Hardware Signal Definitions
I/O Type Signal Name/Description Media Independent Interface (MII) These pins are multiplexed with the GPSI pins and are selected when MII_GSPI_N signal is at VDD. MII Receive Data. Data is transferred from the CX11656 to the O Ot1 MII_RX[3:0] 27, 29, 31, external MAC across these four lines, MII_RX[3:0], one nibble at a 33 time. MII Receive Clock. MII_RXCLK outputs a continuous 25 MHz clock to MII_RXCLK/ 22 O Ot1 GPSI_RXCLK the external MAC. MII Receive Data Valid. When asserted high, MII_RXDV indicates MII_RXDV/ 25 O Ot1 GPSI_TXBSY that the incoming data on the MII_RX[3:0] pins are valid. MII Receive Error. When asserted high, MII_RX_ER indicates to the MII_RX_ER/ 18 O Ot1 GPSI_RXD external MAC that an error has occurred during the frame reception. MII Transmit Data. Data is transferred to the CX11656 from the 4, 6, 8 MII_TX[3:1] I It external MAC across these four lines (MII_TX[3:0]) one nibble at a MII_TX0/GPSI_TXD 11 time. MII Transmit Clock. MII_TXCLK outputs a continuous 25MHz clock to MII_TXCLK/ 14 O Ot1 GPSI_TXCLK the external MAC. MII Transmit Enable. This signal indicates to the CX11656 that valid MII_TXEN/ 12 I It GPSI_TXEN data is present on the MII_TX[3:0] pins. MII Transmit Error. MII_TX_ER is activated by the external host MII_TX_ER 16 I It controller when an error condition is detected during packet transmission. The CX11656 will ignore any MII transmission within which MII_TX_ER is asserted. MII_TX_ER is ignored if MII_TXEN is not asserted. MII Carrier Sense. When asserted high, MII_CRS indicates to the MII_CRS/ 42 O Ot1 GPSI_RXEN external host that traffic is present on the powerline and the host should wait until the signal goes invalid before sending additional data. This signal is an asynchronous output signal. MII Collision Detect. This signal indicates to the external host that a MII_COL/ 40 O Ot1 GPSI_COL collision has occurred on the MII interface. This signal is an asynchronous output signal. MII Management Data Interface (MDI) These pins are multiplexed with the SPIS_SDO and SPIS_SCLK signals and are selected when MDI_SPIS_N is at VDD. MII Management Data Output. MII_MDIO is the bidirectional signal MII_MDIO/ 135 I/O It/Ot1 SPIS_SDO that carries the data for the Management Data Interface. MII Management Data Clock. MII_MDCLK is the clock reference for MII_MDCLK/ 133 I It SPIS_SCLK the MII_MDIO signal. Signal Name Pin I/O
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CX11656 HomePlug 1.0 PHY Data Sheet
Table 2-2. CX11656 PHY Hardware Signal Definitions (Continued)
I/O Type Signal Name/Description General Purpose Serial Interface (GPSI) These pins are multiplexed with the MII pins and are selected when MII_GSPI_N signal is at VSS. GPSI Receive Data. GPSI_RXD carries data received from the MII_RX_ER/ 18 O Ot1 GPSI_RXD powerline and delivers to the external host. Data is driven on the falling edge of the GPSI_RXCLK. GPSI Receive Clock. GPSI_RXCLK is the timing reference for the MII_RXCLK/ 22 O Ot1 serial data transfer from the CX11656 to the external host. This clock GPSI_RXCLK operates at 10 MHz. GPSI Transmit Data. GPSI_TXD carries data transmitted from the MII_TX0/GPSI_TXD 11 I It external host to the CX11656 for transmission over the powerline. GPSI_TXD Data is latched on the falling edge of the GPSI_TXCLK. GPSI Transmit Clock. This signal is the timing reference for the serial MII_TXCLK/ 14 O Ot1 GPSI_TXCLK data transfer from the external host to the CX11656. This clock operates at 10 MHz. GPSI Receive Enable. When asserted high, GPSI_RXEN indicates MII_CRS/ 42 O Ot1 GPSI_RXEN valid data is on the GPSI_RXD line. GPSI Transmit Enable. When asserted high, GPSI_TXEN indicates MII_TXEN/ 12 I It GPSI_TXEN when the external host is providing valid data on GPSI_TXD. GPSI Transmit Busy. GPSI_TXBSY is asserted within 120 GPSI MII_RXDV/ 25 O Ot1 GPSI_TXBSY clocks after GPSI_TXEN indicates a TX frame is being sent by the local host. GPSI_TXBSY stays true until the entire TX frame is loaded into an internal buffer AND a new buffer is allocated to the GPSI TX interface. This signal should be monitored by the GPSI TX host. A new GPSI TX frame should not be sent until GPSI_TXBSY returns to false to prevent TX buffer overflows. GPSI_TXBSY is an asynchronous output signal. GPSI Collision Detect. GPSI_COL is driven false in GPSI mode. MII_COL/ 40 O Ot1 GPSI_COL SPI Slave Port Selected when MDI_SPIS_N signal is at VSS. SPI Slave Data Out. SPIS_SDO is the SPI data from the CX11656 to MII_MDIO/ 135 O Ot1 SPIS_SDO the external host. SPI Slave Data In. SPIS_SDI is the SPI data from the external host MDI_ADRSEL[1]/ 137 I It SPIS_SDI to the CX11656. This pin is shared with the MDI_ADRSEL[1]. SPI Slave Clock. SPIS_SCLK is the timing reference signal for MII_MDCLK/ 133 I It SPIS_SCLK SPI_SDI and SPI_SDO. SPI Slave Chip Select. When asserted low, SPIS_CS_N enables SPI MDI_ADRSEL[0]/ 139 I It SPIS_CS_N data transfers on the CX11656. This pin is shared with the MDI_ADRSEL[0]. SPI Master Port (Configuration PROM Interface) SPI Master Data Out. SPI_DO is the CX11656 configuration data SPI_DO 59 O Ot1 from the CX11656 to the external E 2 PROM. SPI Master Data In. SPI_DI is the CX11656 configuration data from SPI_DI 57 I It the external E 2 PROM to the CX11656. SPI Master Clock. SPI_CLK is the timing reference signal for SPI_DI SPI_CLK 54 O Ot1 and SPI_DO. SPI Master Chip Select. When asserted high, SPI_CS enables data SPI_CS 52 O Ot1 transfers on the SPI Master Interface. LED Control Collision Detection. LED0_N is asserted low for 9-10 ms upon LED0_N 61 O Ot1 detection of a collision. LED1Activity Detection. LED1_N is asserted low for 9-10 ms upon LED1_N 63 O Ot1 the receipt of a properly addressed unicast or broadcast frame or the transmission of a frame. Link Detection. LED2_N is asserted low when initialization is LED2_N 65 O Ot1 complete successfully and "network" is established. Signal Name Pin I/O
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CX11656 HomePlug 1.0 PHY Data Sheet
Table 2-2. CX11656 PHY Hardware Signal Definitions (Continued)
Signal Name ADC_CLK DAC_CLK TX_EN RX_EN ADIO[9:0] Pin 71 74 76 77 94, 93, 92, 90, 87, 86, 84, 82, 81, 80 106, 105, 103, 102, 100, 98, 97, 96 67 I/O O O O O I/O I/O Type Signal Name/Description Analog Front End Interface ADC Clock. ADC clock output to the Analog Conversion IC. Ot1 DAC Clock. DAC clock output to the Analog Conversion IC. Ot1 Analog Front End Transmit Enable. Transmit Enable signal Ot1 Analog Front End Receive Enable. Receive Enable signal Ot1 Analog/Digital I/O. ADC and DAC Data. Multiplexed parallel interface It/Ot12 to Analog Conversion IC.
AGC[7:0]
O
Ot1
AGC Gain Select. Gain control driven by the CX11656 to set the AGC level.
ADC_CAL
O
AGCENC_N
69
I
TCK TDI TMS TDO TRST_N
114 120 124 116 129
I I I O I
RESET_N CLKIN
44 49
I I
CLKOUT MDI_ADRSEL[1]/ SPIS_SDI, MDI_ADRSEL[0]/ SPIS_CS_N MDI_SPIS_N
48 137, 139
O I
126
I
MII_GPSI_N
141
I
TEST1 TEST2 NC
111 112 131
I I
ADC Calibrate. This pin must remain low during normal operation of the ADC. It is pulsed high to request a calibration cycle. The ADC_CAL minimum pulse width is 4 clock cycles. While this signal is high the ADC calibration registers are cleared and the calibration control circuitry is reset. The ADC_CAL pulse will go high 217 clock cycles (2.6 ms) after power on reset drops, and will remain high for the required 4 clock cycles. AGC Encode. An inactive signal (logic 1) applied to this input selects It unitary AGC format. An active signal (logic 0) applied to this input selects encoded AGC format. Test Access Port (Reserved) Test Clock. Test Clock for the IEEE 1149.1 JTAG Port. It Test Data In. Data In for the IEEE 1149.1 JTAG Port. It Test Mode Select. Test Mode Select for the IEEE 1149.1 JTAG Port. It Test Data Out. Data Out for the IEEE 1149.1 JTAG Port. Ot1 Test Reset. This pin will be used to reset the TAP controller. It should It be connected to ground when the JTAG port is not in use. System Control Reset. Resets logic circuitry, but not clock circuitry. Reset is active low It and should be held low for a minimum of 100 ns. Clock Input. 100 MHz clock input driven by an external oscillator or Ix AFE. Note: CLKIN connects directly to the +1.8 V core of the IC and does not connect to the +3.3 V I/O ring. Therefore, this pin is not +3.3 or 5 V tolerant. Clock Output. 100 MHz clock output. This pin should be left as NO Ox CONNECT. MDI PHY Address Selection. MDI_ADRSEL[1:0] is the address It select used to compare against the upper two bits of the MDI Address. These pins share function with SPIS_SDI and SPIS_CS_N and should be pulled-up or down with external resistors to set the appropriate value which is read by the CX11656 during power up. Management Data Interface/Serial Peripheral Interface Slave It Select. When asserted low, MDI_SPIS_N selects which PHY management signals are active. Media Independent Interface/General Purpose Serial Interface It Select. When asserted low, MII_GPSI_N selects which PHY data interface signals are active. Factory Test Pin 1. Tie to I/O Ground. It Factory Test Pin 2. Tie to I/O Ground. It No Connect. Ot1
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CX11656 HomePlug 1.0 PHY Data Sheet
Table 2-2. CX11656 PHY Hardware Signal Definitions (Continued)
Signal Name VDD_C Pin 1, 2, 7, 13, 17, 23, 24, 28, 32, 37, 38, 43, 50, 53, 60, 68, 73, 78, 99, 104, 109, 115, 121, 122, 123, 125, 132, 140 5, 10, 19, 20, 26, 30, 34, 36, 41, 46, 47, 55, 56, 58, 62, 66, 72, 75, 85, 88, 101, 108, 113, 117, 118, 119, 127, 128, 134, 138, 143, 144 3, 39, 64, 79, 95, 110, 136 9, 35, 45, 70, 83, 107, 142 15, 51, 91 21, 89, 130 I/O P I/O Type PWR Power Supplies +1.8 V Digital Power Signal Name/Description
VSS_C
G
GND
Digital Ground
VDD_IO
P
PWR
+3.3 VI/O Power
VSS_IO
G
GND
I/O Ground
VDD_Q VSS_Q
P G
PWR GND
+3.3 V Quiet Power. Connect to +3.3 V I/O Power Quiet Ground. Connect to I/O Ground
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CX11656 HomePlug 1.0 PHY Data Sheet
2.2
CX11656 PHY Electrical and Environmental Specifications
DC electrical characteristics are listed Table 2-3. Operating conditions are specified in Table 2-4. Absolute maximum ratings are stated in Table 2-5. Power consumption is listed in Table 2-6.
Table 2-3. CX11656 PHY DC Electrical Characteristics
Parameter Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Input Current Symbol VIH VIL VOH VOL Min. 2.0 - 2.4 - Typ. - - - - Max. - 0.8 - 0.4 Units VDC VDC VDC VDC Test Conditions
IOH = -1 mA IOH = 1 mA
II -15 - 15 A Supply Current IDD 370 mA Supply Current ICC - 25 mA Note: Any signal applied to the CX11656 clock pin (CLKIN) should not exceed +1.8 V.
Table 2-4. CX11656 PHY Operating Conditions
Parameter Core Supply Voltage I/O Supply Voltage Operating Temperature Symbol VDD_C VDD_IO TA Min 1.7 3.0 0 Typ 1.8 3.3 Max 1.9 3.6 +70 Units VDC VDC C
Table 2-5. CX11656 PHY Absolute Maximum Ratings
Parameter Core Supply Voltage I/O Supply Voltage Input Voltage Storage Temperature Range Analog Inputs Voltage Applied to Outputs in High Impedance (Off) State Symbol VDD_C VDD_IO VIN TSTG VIN VHZ Limits -0.35 to +1.95 -0.35 to +3.65 -0.35 to (VDD +0.35) -55 to +125 -0.35 to (VDDA + 0.35) -0.35 to (VDDA +0.35) Units VDC VDC VDC C VDC VDC
Table 2-6. CX11656 PHY Power Consumption
Mode VDD_C VDD_IO Test conditions: Typ. Max. Typ. Current Current Power (mA) (mA) (mW) TBD TBD TBD TBD TBD TBD VDD_C = +1.8 VDC for typical values; +1.9 VDC for maximum values. VDD_IO = +3.3 VDC for typical values; +3.465 VDC for maximum values. Max. Power (mW) TBD TBD
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CX11656 HomePlug 1.0 PHY Data Sheet
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CX11656 HomePlug 1.0 PHY Data Sheet
3.
CX11656 Functional Description
The interfaces that provide data, status, and control to and from the CX11656 include: * * * * * * External host interface provided via the Media Independent Interface (MII) format (described by IEEE 802.3u, Clause 22) or a General Purpose Serial Interface (GPSI) Management control provided via the Management Data Interface (MDI) or the Serial Peripheral Interface (SPI) Analog Front End interface LEDs indicating network status Optional EEPROM interface providing a path to initialize the CX11656 The JTAG port implements the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
A block diagram of the CX11656 PHY is shown in Figure 3-1. Figure 3-1. CX11656 PHY Block Diagram
LEDs
CX11656
ROM ROM
MDI or SPI
Configuration Registers
RISC uProcessor Core
Link Sequencer
PHY Seq PHY Core AFE Logic
ADIO[9:0]
MDII or GPSI
AGC [7:0]
MII/GPSI Interface
Interface DMA
Arbiter
PHY DMA
FIFOs
TEST
JTAG
Buffer RAM
EEPROM
SPI Master Interface Block MAC PHY
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CX11656 HomePlug 1.0 PHY Data Sheet
3.1
MII Data Interface with MDI Control
Data communication between the CX11656 and the external host controller is provided via the Media Independent Interface (MII) or a reduced General Purpose Serial Interface (GPSI). The MII_GPSI_N select pin is included on the chip interface to configure the CX11656 in either MII mode or GPSI mode. Access to the CX11656's internal MII status and control registers is via the Management Data Interface or a SPI interface. The MDI_SPIS_N select pin is included on the chip interface to configure the CX11656 in either MDI mode or SPI mode. The information that follows describes the MII communication interface along with the MDI management interface as a typical example. The MII data interface with MDI control is illustrated in Figure 3-2.
Figure 3-2. MII Data Interface with MDI Control
CX11656
MII_RX(3:0) MII_RXCLK MII_RX_ER MII_RXDV MII_CRS MII_COL
External Host Controller
MII_TX(3:0) MII_TXCLK MII_TX_ER MII_TXEN MII_MDCLK MII_MDIO
Interface Block
PowerPacket MAC
PowerPacket PHY
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CX11656 HomePlug 1.0 PHY Data Sheet
3.1.1
MII Interface
MII is an industry standard, multi-vendor, interoperable interface between separate MAC and PHY devices. It provides a simple interconnection between the CX11656 and IEEE802.3 Ethernet MAC controllers (commonly referred to as external host controllers in this document) available from a variety of IC suppliers. The MII consists of separate 4bit data paths for transmit and receive data along with carrier sense and collision detection. Data is transferred between the MAC and PHY over each 4-bit data path synchronous with a clock signal supplied to the host by the CX11656. The MII interface also provides a 2-wire bidirectional serial management data interface (MDI). This interface provides access to the status and control registers in the CX11656.
3.1.1.1
MII Timing Diagram
The transmission behavior of the MII interface is illustrated in Figure 3-3. The receive behavior of the MII interface is illustrated in Figure 3-4. An unsuccessful attempt to transmit a packet, resulting in a collision, is illustrated in Figure 3-5. The MII receive timing is illustrated in Figure 3-6. The MII transmit timing is illustrated in Figure 3-7. The MII DC characteristics are listed in Table 3-1. Note: MII_CRS is asynchronous to MII_TXCLK.
Figure 3-3. MII TX Waveform
MII_TXCLK
MII_CRS
MII_TXEN
MII_TXD[3:1], MII_TX0
DATA
DATA
DATA
DATA
MII_COL
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CX11656 HomePlug 1.0 PHY Data Sheet Figure 3-4. MII RX Waveform
MII_RXCLK
MII_CRS
MII_RXDV
MII_RX[3:0]
DATA
DATA
DATA
DATA
Figure 3-5. MII TX with Collision Based on RX Activity
MII_CRS
MII_TXEN
MII_RXDV
MII_COL
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CX11656 HomePlug 1.0 PHY Data Sheet
Figure 3-6. MII Receive Timing
MII_RXCLK tMII_RVAL MII_RXD[3:0], MII_RXVD, MII_RX_ER, MII_COL, MII_CRS
DATA
102069_010
Figure 3-7. MII Transmit Timing
MII_TXCLK tMII_TSU tMII_TH MII_TXD[3:1], MII_TX0, MII_TXEN, MII_TX_ER
DATA
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Table 3-1. MII DC Characteristics
Parameter Symbol tMII_RVAL Parameter Name Test Condition Receive Timing Measured from Vilmax = 0.8V or Measured from Vihmin = 2.0V Transmit Timing tMII_TSU tMII_TH MII_TXEN, MII_TX0, MII_TX[3:1] setup to MII_TXCLK MII_TXEN, MII_TX0, MII_TX[3:1] hold to MII_TXCLK Measured from Vilmax = 0.8V or Measured from Vihmin = 2.0V Measured from Vilmax = 0.8V or Measured from Vihmin = 2.0V 8 0 ns ns Min. Max. Unit
MII_RX[3:0], MII_RXDV valid from MII_RXCLK
0
25
ns
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CX11656 HomePlug 1.0 PHY Data Sheet
3.1.1.2
MII Signal Descriptions
The following description references Clause 22, Media Independent Interface specification, used in the 100 Mbps half-duplex mode. The MII is used as a data channel that transfers data back and forth with flow controlled by the carrier sense signal (MII_CRS). MII_TXCLK and MII_RXCLK. The CX11656 generates a stable, continuous 25 MHz square wave that is supplied on MII_TXCLK and MII_RXCLK. These clocks provide the timing reference for the transfer of the MII_TXEN and MII_TX signals, as well as MII_RX, MII_RX_ER, and MII_RXDV. MII_RX_ER. MII_RX_ER is activated when the CX11656 detects an error in the receive stream as a result of decoding. MII_TX_ER. MII_TX_ER is activated by the external host controller when an error condition is detected during packet transmission. The CX11656 will ignore any MII transmission within which MII_TX_ER is asserted. MII_TX_ER is ignored if MII_TXEN is not asserted. MII_TXEN. MII_TXEN from the external host provides the framing for the Ethernet packet. An active MII_TXEN indicates to the CX11656 that data on MII_TX[3:0] should be sampled using MII_TXCLK. MII_TX[3:0]. MII_TX[3:0] contains the data to be transmitted and transitions synchronously with respect to MII_TXCLK. MII_TX[0] is the least significant bit. It is generally assumed that the data will contain a properly formatted Ethernet frame. That is, the first bits on MII_TX[3:0] correspond to the preamble, followed by SFD and the rest of the Ethernet frame (DA, SA, length/type, data, CRC). MII_RXDV. MII_RXDV is asserted by the CX11656 to indicate that the CX11656 has decoded receive data to present to the external host. MII_RX[3:0]. MII_RX[3:0] contains the data recovered from the medium by the CX11656 and transitions synchronously with respect to MII_RXCLK. MII_RX[0] is the least-significant bit. The CX11656 formats the frame such that the external MAC will be presented with expected preamble plus SFD. MII_CRS. MII_CRS is used to tell the external host when the CX11656 is available for sending a packet. MII_CRS is asynchronous to MII_TXCLK. When a packet is being transmitted, CRS is held high. CRS will go low whenever the CX11656 is ready to accept another packet. On transmit, the CX11656 asserts MII_CRS some time after MII_TXEN becomes active, and drops MII_CRS after MII_TXEN goes inactive AND when the CX11656 is ready to receive another packet from the external host for transmission. When MII_CRS has been negated for at least 900ns, the external MAC may assert MII_TXEN again if there is another packet to send. This differs from nominal behavior of MII_CRS in that MII_CRS can extend past the end of the packet by an arbitrary amount of time, while the CX11656 is gaining access to the channel and transmitting the packet. MII_CRS does not affect the receive side of the channel. Once packets start arriving from the powerline medium and begin transmission to the external host controller over the MII interface, the external host must be ready to receive or the packet can be lost. Note that external MACs programmed to run in 100 Mbps mode do not use a jabber timeout, so there is no timing restriction on how long MII_CRS can be asserted.
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CX11656 HomePlug 1.0 PHY Data Sheet
Figure 3-8. MII Flow Control Overview, Part 1
32 ns (32 bit times) 32 ns (32 bit times) 32 ns (32 bit times)
MII_CRS
32 ns (32 bit times)
MII_TXEN
MII_TXD[3:1], MII_TX0
P
P
Internal TX buffer available pulse
MII_RX[3:0]
P
P
P
MII_RXDV
External RX buffer available pulse
MII_COL Case 1
TX only
Case 2
RX only
Case 3
RX while TX, delayed TX buf avail
Case 4
RX while no TX buf avail
Case 4
TX buf avail
102069_012
Figure 3-9. MII Flow Control Overview, Part 2
MII_CRS
MII_TXEN
MII_TXD[3:1], MII_TX0
P
P
P
MII_RX[3:0]
P
MII_RXDV
MII_COL Case 1
TX only
Case 7
TX overrun, frame dropped
Case 8
Collision
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CX11656 HomePlug 1.0 PHY Data Sheet
3.1.1.3
MII Frame Structure
The frame structure transmitted on the MII or GPSI interface is the following sequence of fields:
Interframe Gap Preamble Start Frame Delimiter Data
Interframe Gap
A period on the MII interface during which no data activity occurs on the MII.
Preamble
Begins a frame transmission that consists of 7 octets with the following bit values: 10101010 10101010 10101010 10101010 10101010 10101010 10101010 The preamble is stripped by the CX11656 when transmitting (the preamble is not transmitted on the PLC medium) and pre-pended by the CX11656 when receiving.
Start Frame Delimiter
Indicates the start of a frame and follows the preamble. The SFD bit sequence is 10101011. The start frame delimiter is stripped by the CX11656 when transmitting (the SFD is not transmitted on the PLC medium) and pre-pended by the CX11656 when receiving
Data
Data sent over the MII interface consists of N bytes of data transmitted as 2N nibbles. The de-assertion of the MII_TXEN signals the End Of Frame (EOF) for data transmitted on the MII_TX[3:0] pins. Likewise, the de-assertion of the MII_RXDV signals the EOF for data transmitted on MII_RX[3:0]. Figure 3-10. Partition of Serial Bit Stream to Nibble Stream
MACs Serial Bit Stream
LSb First nibble LSb D0 D1 D2 D3
101409_014
D0
D1
D2
D3
D4
D5
D6
D7
MSb Second nibble
MII Nibble Stream
MSb
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CX11656 HomePlug 1.0 PHY Data Sheet
3.1.2
MDI Control Interface
The Management Data Interface connects the external host to the CX11656 for purposes of controlling the CX11656 and gathering status. A specific frame format and protocol definition exists for exchanging management frames over this interface. A register definition exists as well that specifies a basic register set with an extension mechanism. The CX11656 implements the basic register set only. The MDI receive timing is illustrated in Figure 3-11. The MDI transmit timing is illustrated in Figure 3-12. The MDI DC characteristics are listed in Table 3-2.
Figure 3-11. MDI Receive Timing
MII_MDCLK tMII_RVAL MII_MDIO
DATA
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Figure 3-12. MDI Transmit Timing
MII_MDCLK tMII_TSU tMII_TH MII_MDIO
DATA
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Table 3-2. MI DC Characteristics
Parameter Symbol tMI_RVAL Parameter Name Test Condition Receive Timing Measured from Vilmax = 0.8V or Measured from Vihmin = 2.0V Transmit Timing Measured from Vilmax = 0.8V or Measured from Vihmin = 2.0V Measured from Vilmax = 0.8V or Measured from Vihmin = 2.0V Min. Max. Unit
MII_MDIO valid from MII_MDCLK MII_MDIO setup to MII_MDCLK MII_MDIO hold to MII_MDCLK
0
300
ns
tMI_TSU tMI_TH
10 10
ns ns
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CX11656 HomePlug 1.0 PHY Data Sheet
3.1.2.1
MDI Signal Descriptions
Management Data Input/Output
MII_MDIO is a bi-directional signal that is used to transfer status and control information between the CX11656 and the external host. Control information is driven by the external host synchronously with respect to MII_MDCLK and is sampled synchronously by the CX11656. Status information is transferred from the CX11656 to the external host in the same manner.
Management Data Clock
MII_MDCLK is sourced by the external host as the timing reference for transfer of information on the MII_MDIO signal.
3.1.3
MII Management Register Set
The IEEE 802.3u mandated management data registers for control and status are accessible via the Management Data Interface (MDI). These registers are also accessible via the industry supported serial peripheral interface. The MDI Port will only respond to addresses 0xbXX000 when the XX field (MSbits of the MDI address) match the state of the MDI_ADRSEL[1:0] input signals. These registers can also be accessed from the SPI Slave port when the MDI_SPIS_N select line has been tied low to select the SPI Slave port. Table 3-3 summarizes the Power Line Control and Status Register. The MDI Frame Structure is shown in Figure 3-13. Table 3-3. Powerline Control and Status Register (PLCSR) Summary
PLCSR 0 1 Register Name Control Register Status Register MII Mandated X X
Figure 3-13. MDI Frame Structure
READ WRITE PRE 1...1 1...1 ST 01 01 OP 10 01 PHYAD AAAAA AAAAA RAGAD RRRRR RRRRR TA Z0 10 Data DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD Idle Z Z
3.1.3.1
PRE (Preamble)
At the beginning of each MDI transaction, the external host shall send a sequence of 32 contiguous logic "1" bits on the MDIO signal so the CX11656 can establish synchronization. The CX11656 needs to observe this 32 bit sequence on the MII_MDIO signal before it responds to any transaction.
3.1.3.2
ST (Start of Frame)
Indicated by a "01" pattern.
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CX11656 HomePlug 1.0 PHY Data Sheet
3.1.3.3
OP (Operation Code)
READ is indicated by "10". WRITE is indicated by "01".
3.1.3.4
PHYAD (PHY Address)
The PHY Address is 5 bits, allowing up the 32 unique PHY addresses. The CX11656 will respond to PHY addresses indicated by 0bXX000. The "XX" bits of the PHY address are controlled by the CX11656 interface pins MDI_ADRSEL(0:1). This allows the designer to assign the CX11656 to one of 4 unique PHY addresses.
3.1.3.5
REGAD (Register Address)
The Register Address is 5 bits and is used to index the maximum of 32 individual registers in the MDI address space. The CX11656 only implements the two mandated MII registers. 0b00000 will index the MII Control Register and 0b00001 will index the MII Status Register.
3.1.3.6
TA (Turnaround)
The turnaround time is a 2-bit time spacing between the Register Address field and the Data field to avoid contention during a read transaction. For reads, both the external host and the CX11656 remain three-stated for the first bit time. The CX11656 will drive a "0" during the second bit time. For writes, the external host drives a "1" for the first bit time and a "0" bit for the second bit time.
3.1.3.7
Data
The data field is 16 bits. The first data bit transmitted and received is bit 15 of the register being addressed.
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CX11656 HomePlug 1.0 PHY Data Sheet
3.2
GPSI Interface with SPI Control
The General Purpose Serial Interface (GPSI) is a flexible, bi-directional serial interface that can be utilized in place of the MII. It provides a straightforward interface to a communications controller through a synchronous serial data stream for transmit and receive data. When using the GPSI interface, the management interface can either be MDI or SPI, selected by the MDI_SPIS_N pin. The information that follows describes the GPSI communication interface along with the SPI management interface as a typical example. The GPSI interface signals are shown in Figure 3-14.
Figure 3-14. GPSI Data Interface with SPI Control
CX11656
GPSI_RXD GPSI_RXCLK GPSI_RXEN GPSI_COL GPSI_TXBSY GPSI_TXD
External Host Controller
GPSI_TXCLK GPSI_TXEN
Interface Block
PowerPacket MAC
PowerPacket PHY
SPIS_SDO SPIS_SDI SPIS_SCLK SPIS_CS_N
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3.2.1
GSPI Interface
GPSI is an interoperable interface providing a simple interconnection between the CX11656 and embedded microcontrollers. Data is transferred between the host controller and the CX11656 over separate 1-bit transmit and receive data paths synchronous with clock signals supplied to the host by the CX11656.
3.2.1.1
GPSI Timing Diagrams
The figures below show the transmission and reception of packets and the corresponding behavior of the GPSI interface. A packet is transferred from the host when GPSI_TXEN goes high. An unsuccessful attempt is made to transmit a packet in Case 5. The received packet is passed to the host when GPSI_RXEN is high. The GSPI flow control is illustrated in Figure 3-15. The GSPI transmit and receive timing are illustrated in Figure 3-16 and Figure 3-17, respectively.
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CX11656 HomePlug 1.0 PHY Data Sheet Figure 3-15. GPSI Flow Control
GPSI_TXEN
GPSI_TXD
P
P
P
P
GPSI_TXBSY
Internal TX buffer available pulse
GPSI_RXEN
GPSI_RXD
P
P
Internal RX buffer available pulse
GPSI_COL Case 1
TX only
Case 2
RX only
Case 3
RX & TX
Case 4
TX, buf avail
Case 5
TX, no buf avail, frame dropped 102069_019
Figure 3-16. GPSI Transmit Timing
tGPSI_TPER GPSI_TXCLK tGPSI_TDELAY GPSI_TXD tGPSI_TDELAY tGPSI_THIGH
GPSI_TXEN tGPSI_TTXBSYH GPSI_TXBSY
GPSI_COL
102069_020
Figure 3-17. GPSI Receive Timing
tGPSI_RPER GPSI_TXCLK tGPSI_RSU GPSI_RXD tGPSI_RDH GPSI_RXEN tGPSI_RLOW tGPSI_RRXENH tGPSI_RHIGH
GPSI_COL
102069_021
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CX11656 HomePlug 1.0 PHY Data Sheet
3.2.1.2
GPSI DC Characteristics
The GSPI DC characteristics are listed in Table 3-4.
Table 3-4. GPSI DC Characteristics
Parameter Symbol tGPSI_RPER tGPSI_RHIGH tGPSI_RLOW tGPSI_RSU tGPSI_RDH tGPSI_RRXENH tGPSI_TPER tGPSI_THIGH tGPSI_TDELAY tGPSI_TRXENH Parameter Name Receive Timing GPSI RXCLK Period GPSI RXCLK High Time GPSI RXCLK Low Time GPSI_RXD and GPSI_RXEN Setup to GPSI_RXCLK GPSI_RXD Hold after GPSI_RXCLK GPSI_RXEN Hold after GPSI_RXCLK Transmit Timing GPSI TXCLK Period GPSI TXCLK High Time GPSI_TXD and GPSI_TXEN Delay from GPSI_TXCLK GPSI_RXEN Hold after GPSI_TXEN @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V 99.99 40 40 15 15 0 99.99 40 0 0 100.01 60 70 100.01 60 60 ns ns ns ns ns ns ns ns ns ns Test Condition Min Max Unit
3.2.1.3
GPSI Signal Descriptions
GPSI_TXCLK and GPSI_RXCLK: The CX11656 generates a stable, continuous 10 MHz square wave that is supplied on GPSI_TXCLK and GPSI_RXCLK. These clocks provide the timing reference for the transfer of the GPSI_TXEN and GPSI_TXD signal, as well as GPSI_RXEN and GPSI_RXD. GPSI_RXD: GPSI_RXD contains the data recovered from the medium by the CX11656 and transitions synchronously with respect to GPSI_RXCLK. The CX11656 properly formats the frame such that the external host controller will be presented with the expected preamble plus SFD. GPSI_RXEN: GPSI_RXEN is asserted by the CX11656 to indicate that the CX11656 has decoded receive data to present to the external host controller. GPSI_TXBSY: GPSI_TXBSY is an optionally used signal to tell the external host controller when the CX11656 is available for sending packets. When a packet is being transmitted, GPSI_TXBSY is held high. GPSI_TXBSY will go low whenever the CX11656 is ready to send another packet. If this signal is not used, the transmitting logic must pace the packet transmissions to ensure that no packets are lost due to buffer overflow. On transmit, the CX11656 asserts GPSI_TXBSY sometime after GPSI_TXEN becomes active, and drops GPSI_TXBSY after GPSI_TXEN goes inactive AND when the CX11656 is ready to accept another packet for transmission. When GPSI_TXBSY falls, the external host controller may assert GPSI_TXEN again if there is another packet to send. GPSI_TXBSY does not affect nor reflect the receive side of the channel. Once packets start arriving off of the powerline medium and begin transmission to the external host controller over the GPSI interface, the external host controller MUST be ready to receive or the packet can be lost. GPSI_TXEN: GPSI_TXEN from the external host provides the framing for the Ethernet packet. An active GPSI_TXEN indicates to the CX11656 that data on GPSI_TXD should be sampled using GPSI_TXCLK.
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CX11656 HomePlug 1.0 PHY Data Sheet GPSI_TXD: GPSI_TXD contains the data to be transmitted and transitions synchronously with respect to GPSI_TXCLK. It is generally assumed that the data will contain a properly formatted Ethernet frame (see MII Frame Structure above). That is, the first bits on GPSI_TXD correspond to the preamble, followed by Start Frame Delimiter (SFD) and the rest of the Ethernet frame (DA, SA, length/type, data, CRC).
3.2.2
SPI Slave Port Interface
The CX11656 implements a SPI Slave port that when connected to an external host controller containing a SPI Master, can be used to control access to the two configuration registers. The SPI Slave port uses a 16- bit control field (MSb first) consisting of a 6-bit command field, a 5-bit reserved field, and a 5-bit address field to control access to the two configuration registers detailed above (Table 3-5). Following the control field, the 16-bit register contents are written or read based on the command field.
Table 3-5. SPI Slave Command Summary
Register function 15 5 L L L L 14 13 12 11 Command Field 4 3 2 1 H L L L L L L L L L L L L H H H 10 0 L H L H Control Field 9 87 6 5 Reserved Field 4 3 2 1 H L L L H H H L L L L L L L L L 4 0 L L L L 2 1 0 Address Field 4 3 2 1 L L L L L L L L L L L L L L L L 3
Write PLCSR0 (Control Register) Read PLCSR0 (Control Register) Write PLCSR1 (Status Register) Read PLCSR1 (Status Register)
0 L L H H
CX11656 SPECIFICATION
3.2.2.1
SPI Slave Port Signal Timing
SPI Slave Port timing is illustrated in Figure 3-18.
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CX11656 HomePlug 1.0 PHY Data Sheet Figure 3-18. SPI Slave Port Timing
tSPIS_LOW SPIS_CLK tSPIS_SU SPIS_DI tSPIS_H SPIS_DO
MSB OUT BITS 6-1 LSB OUT MSB IN BITS 6-1 LSB IN
tSPIS_HIGH
tSPIS_SDOSV SPIS_CS_N tSPIS_CSLEAD
tSPIS_CSLAG
102069_022
3.2.2.2
SPI Slave Port DC Characteristics
The SPI Slave Port DC characteristics are listed in Table 3-6.
Table 3-6. SPI Slave Port DC Characteristics
Parameter Symbol tSPIS_F tSPIS_HIGH tSPIS_LOW tSPIS_SDOVD tSPIS_CSLEAD tSPIS_CSLAG tSPIS_SU tSPIS_H Parameter Name Test Condition Min Max 2.1 @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V 400 400 0 500 1500 200 200 500 Unit MHz ns ns ns ns ns ns ns
SPIS_SCLK Frequency SPIS_SCLK High Time SPIS_SCLK Low Time SPIS_SDO Valid Output Delay from SPIS_SCLK SPIS_CS Lead to SPIS_SCLK SPIS_CS Lag from SPIS_SCLK SPIS_SDI Setup Time to SPIS_SCLK SPIS_SDI Hold Time to SPIS_SCLK
3.3
Clocks
The CX11656 runs from a single 100 MHz oscillator input and generates a 50 MHz clock to feed the ADC, a 50 MHz clock to feed the DAC, the 25 MHz MII clock, and the 10 MHz GPSI clock. The 100 MHz clock input directly feeds the clock distribution network that clocks up to 60% of the digital logic. Note: Both CLKIN and CLKOUT connect directly to the +1.8 V core of the IC and do not connect to the +3.3 V I/O ring. Therefore these pins are not +3.3 V or +5 V tolerant.
The oscillator must have 25 PPM RMS maximum tolerance including initial accuracy, temperature/voltage range and 5 years of aging. This oscillator must have a symmetry no worse than 40/60, jitter of 75 ps and 4 ns rise and fall time. The oscillator must be rated over the desired temperature range and 10% voltage range. The CX11656 uses a crystal input cell to receive the clock input.
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CX11656 HomePlug 1.0 PHY Data Sheet
3.4
AFE Interface
The CX11656 provides a simple parallel interface to the analog front end (AFE). The analog data is clocked into or out of the CX11656 on a 10-bit bi-directional parallel data bus under control of transmit or receive enable signals and sample clock references provided to the AFE from the CX11656. The CX11656 also provides a parallel byte-wide automatic gain control interface.
3.4.1
ADC/DAC Interface
The CX11656 outputs a sequential stream of digital time samples of the OFDM waveforms for transmission. The digital transmit signal is passed on to the A/D Converter. The ADC digitizes the analog OFDM receive signal for input to the CX11656. The DAC converts digital samples into analog waveforms.
3.4.1.1
ADC/DAC Timing Diagrams
AFE TX and RX activity is illustrated in Figure 3-19. AFE clock waveforms are illustrated in Figure 3-20. AFE transmit and receive timing is illustrated in Figure 3-21 and Figure 3-22, respectively.
Figure 3-19. AFE TX and RX Activity
DAC_CLK
TX_EN
ADIO[9:0]
TX DATA
TX DATA
TX DATA
RX DATA
RX DATA
RX DATA
ADC_CLK
RX_EN
102069_023
Figure 3-20. AFE Clock Waveforms
tAFE_H
2.0 V
DAC_CLK, ADC_CLK
1.5 V 0.8 V
tAFE_L
tAFE_R
tAFE_FT tAFE_PW
102069_024
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CX11656 HomePlug 1.0 PHY Data Sheet Figure 3-21. AFE Transmit Timing Diagram
DAC_CLK tMII_RVAL ADIO[9:0], RX_EN, TX_EN
DATA
102069_025
Figure 3-22. AFE Receive Timing Diagram
ADC_CLK tMII_TSU ADIO[9:0]
DATA
tMII_TH
102069026
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CX11656 HomePlug 1.0 PHY Data Sheet
3.4.1.2
DAC DC Characteristics
The DAC DC characteristics are listed in Table 3-7.
Table 3-7. DAC DC Characteristics
Symbol Number of Bits Data Format Sample Rate VOH VOL tAFE_RVAL High level output voltage Low level output voltage Propagation Delay Time DAC Data Output 1, 2 1, 3 1 DAC Clock Output 1 1 1 1 Parameter Test Conditions Min Typ Max 10 Straight Binary Unit bits MSPS V V ns ns ns ns ps rms
50 2.4 5.0 10 8.2 0.4 15.0 15 2 2 75
tAFE_PW DAC Clock Pulse Width tAFE_R DAC Clock Rise Time tAFE_FT DAC Clock Fall Time tJ DAC Clock Jitter Conditions: 1. VDD = 3.3 V, CL = 15 pF, RL = 1K 2. IOH = -1 mA 3. IOL = 1mA
1647 SPECIFICATION
3.4.1.3
ADC DC Characteristics
The ADC DC characteristics are listed in Table 3-8.
Table 3-8. ADC DC Characteristics
Symbol Number of Bits Data Format Sample Rate ADC Data Input VIH VIL tA tAFE_TSU tAFE_TH High level input voltage Low level input voltage Aperture Delay Time Data Setup Time Data Hold Time ADC Clock Output VOH High level output voltage VOL Low level output voltage tAFE_H ADC/DAC Clock Pulse Width High tAFE_L ADC/DAC Clock Pulse Width Low tAFE_R ADC/DAC Clock Rise Time tAFE_FT ADC/DAC Clock Fall Time tJ ADC/DAC Clock Jitter Conditions: VDD = 3.3 V, CL = 15 pF, RL = 1K 1 1 1 1 1 1 1 2.1 10 10 V 0.9 15 15 2 2 75 V ns ns ns ns ps rms 1 1 1 1 1 2.0 0.8 2.7 3 3 V V ns ns ns Parameter Test Conditions Min Typ Max 10 Straight Binary Unit bits MSPS
50
CX11656 SPECIFICATION
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CX11656 HomePlug 1.0 PHY Data Sheet
3.4.2
AGC Circuitry
The CX11656 receives 10-bit digitized samples from the D/A Converter and uses them to adjust the Switched Gain Amplifier (SGA) gain to maintain optimum signal level at the input of the ADC. The AGC[7:0] control bus is used to pass a Gain Control Value (GCV) to the SGA. If the AGCENC_N input pin is low, the GCV is encoded on pins [3:0] of the AGC[7:0] control bus. If the AGCENC_N input pin is high, the GCV is decoded on pins [7:0] of the AGC[7:0] control bus with pins [7:4] selecting the gain switch setting for the first stage amplifier and pins [3:0] selecting the gain switch setting for the second stage amplifier. RX gain control values are listed in Table 3-9.
Table 3-9. RX Gain Control Values
GCV (AGCENC_N = 0) AGC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 GCV (AGCENC_N = 1) AGC[7:4] AGC[3:0] 000 000 1000 1000 0100 1000 0010 1000 0001 1000 0001 0100 0001 0010 0001 0001 Front End Gain (dB) OFF 0 8 16 24 32 40 48 Notes Mute RX during TX mode
3.4.2.1
AGC DC Characteristics
AGC DC characteristics are listed in Table 3-10.
Table 3-10. AGC DC Characteristics
Symbol Parameter VOH High level output voltage VOL Low level output voltage tR Rise time tF Fall time Conditions: VDD = 3.3 V, CL = 15 pF, RL = 1K Test Conditions 1 1 1 1 Min 2.1 Typ Max 0.9 5 5 Unit V V ns ns
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CX11656 HomePlug 1.0 PHY Data Sheet
3.5
SPI Master Interface
The SPI Master interface gives the system designer the option of providing the CX11656 with the necessary configuration information from a simple, SPI-controlled EEPROM as opposed to supplying this information via MAC management frames (transmitted over the MII interface). The information stored in the EEPROM is intended to initialize the CX11656 with specific information that will not be changed throughout its normal course of operation. For specific features that require real-time control, this information must be provided via the MAC management frames and not from the EEPROM. The EEPROM must be an Atmel AT93C46, or equivalent, programmed in 8-bit mode.
3.5.1
SPI Master Interface Timing
The SPI Master interface signal timing is illustrated in Figure 3-23.
Figure 3-23. SPI Master Interface Signal Timing Diagram
tSPI_HIGH SPIS_CLK tSPI_LOW tSPI_H SPIS_DI
DATA
tSPI_SU
tSPI_DIVD
DATA
tSPI_CSDV
SPIS_DO
tSPI_CSL SPIS_CS_N
102069_027
3.5.2
SPI Master Interface DC Characteristics
The SPI Master interface DC characteristics are listed in Table 3-11.
Table 3-11. SPI Master Interface DC Characteristics
Parameter Symbol tSPI_F tSPI_HIGH tSPI_LOW tSPI_DIVD tSPI_CSVD tSPI_CSL tSPI_SU tSPI_H Parameter Name SPI_SCLK Frequency SPI_SCLK High Time SPI_SCLK Low Time SPI_DI Valid Output Delay from SPI_SCLK SPI_CS Valid Output Delay from SPI_SCLK SPI_CS Low Time SPI_DO Setup Time to SPI_SCLK SPI_DO Hold Time to SPI_SCLK Test Condition Min Max 6.125 90 90 15 15 Unit MHz ns ns ns ns ns ns ns
@ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V
70 70 0 0 1000 50 0
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CX11656 HomePlug 1.0 PHY Data Sheet
3.6
LED Interface
LED interface signals are described in Table 3-12.
Table 3-12. LED Interface Signal Description
Signal LED0_N LED1_N LED2_N Status Collision Activity Link Description LED0_N: Collision Detection. Activates for a duration of 9-10 ms upon detection of a collision. LED1_N: Activity Detection. Activates for a duration of 9-10 ms upon the receipt of a properly addressed unicast or broadcast frame or the transmission of a frame. LED2_N: Link Detection. Turns on when initialization is completed successfully and "network" is established.
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CX11656 HomePlug 1.0 PHY Data Sheet
4.
Package Dimensions
Package dimensions for the 144-pin LQFP are shown in Figure 4-1.
Figure 4-1. Package Dimensions - 144-Pin LQFP
D D1 D2
PIN 1 REF
D
D1 D2
D1
e
b DETAIL A
Dim.
D1
A A1 A2 D D1 D2 L L1 e
Millimeters Min. Max. 1.6 MAX 0.15 0.05 21.75 1.4 REF 22.25
Inches* Max. Min. 0.0630 MAX 0.0020 0.0059 0.0551 REF 0.8563 0.8760 0.7874 REF 0.6890 REF 0.0197 0.0295 0.0394 REF 0.0197 BSC 0.0067 0.0106 0.0043 0.0067 0.0031 MAX
20.0 REF 17.5 REF 0.75 0.5 1.0 REF 0.50 BSC 0.17 0.11 0.27 0.17 0.08 MAX
A
A2
b c Coplanarity
Ref: 144-PIN LQFP (GP00-D252)
c A1 L1 DETAIL A
L
* Metric values (millimeters) should be used for PCB layout. English values (inches) are converted from metric values and may include round-off errors.
PD_LQFP_144
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CX11656 HomePlug 1.0 PHY Data Sheet
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CX11656 HomePlug 1.0 PHY Data Sheet
5.
5.1
Application Designs
Ethernet Router Application
An Ethernet Router application design is illustrated in Figure 5-1. Refer to CX82100 Home Network Processor (HNP) Data Sheet (Doc. No. 101306) for CX82100-41 information.
Figure 5-1. Ethernet Router Application Block Diagram
LEDs LEDs
Powerline
Etherent
CX82100-41 Home Network Processor (HNP)
MII
CX11656 HomePlug 1.0 PHY Transceiver
Analog Front End
Coupler
102069_030
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CX11656 HomePlug 1.0 PHY Data Sheet
5.2
USB Application
A USB application design is illustrated in Figure 5-2.
Figure 5-2. USB Application Block Diagram
LEDs
Powerline
USB
802.3 MAC Controller for USB
MII
CX11656 HomePlug 1.0 PHY Transceiver
Analog Front End
Coupler
102069_031
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CX11656 HomePlug 1.0 PHY Data Sheet
5.3
Embedded Application
An embedded application design is illustrated in Figure 5-3.
Figure 5-3. Embedded Application Block Diagram
LEDs
Powerline
USB
Embedded IC with Integrated 802.3 MAC Controller
MII
CX11656 HomePlug 1.0 PHY Transceiver
Analog Front End
Coupler
102069_032
5.4
ADI-Related Components
For further information regarding the ADI components used in the Analog Front End, please refer to the following ADI data sheets: AD8007/AD8008 - Low Distortion High Speed Amp AD6417 - LC2MOS Precision Mini-DIP Analog Switch AD8016 - Low Power, High Output Current xDSL Line Driver AD9975 - Broadband Modem Mixed-Signal Front End
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NOTES
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